1. general description the 74ahc86-q100; 74ahct86-q100 are high-speed si-gate cmos devices and are pin compatible with low-power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74ahc86-q100; 74ahct86-q100 provid es a 2-input exclusive-or function. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have a schmitt-trigger action ? inputs accept voltages higher than v cc ? for 74ahc86-q100 only: operates with cmos input levels ? for 74ahct86-q100 only: operates with ttl input levels ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74ahc86-q100; 74ahct86-q100 quad 2-input exclusive-or gate rev. 1 ? 5 june 2013 product data sheet table 1. ordering information type number package temperature range name description version 74AHC86D-Q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahct86d-q100 74ahc86pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahct86pw-q100 74ahc86bq-q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74ahct86bq-q100
74ahc_ahct86_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 5 june 2013 2 of 15 nxp semiconductors 74ahc86-q100; 74ahct86-q100 quad 2-input exclusive-or gate 4. functional diagram fig 1. logic symbol mna787 1a 1b 1y 2 1 3 2a 2b 2y 5 4 6 3a 3b 3y 10 9 8 4a 4b 4y 13 12 11 fig 2. logic diagram (one gate) fig 3. iec logic symbol mna788 y a b mna786 3 =1 =1 =1 =1 2 1 6 5 4 8 10 9 11 13 12
74ahc_ahct86_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 5 june 2013 3 of 15 nxp semiconductors 74ahc86-q100; 74ahct86-q100 quad 2-input exclusive-or gate 5. pinning information 5.1 pinning 5.2 pin description 6. functional description [1] h = high voltage level; l = low voltage level. (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration so14, tssop14 fig 5. pin configuration dhvqfn14 $ + & |